The following poster about the QPACE processor was presented at the Lattice Conference 2009 in Beijing China. It presents an overview of the design and implementation of the QPACE Network Processor. The Network Processor implements a standard Ethernet network and a high-speed communication network that allows for a tight coupling of the processing nodes. By using an FPGA we have the flexibility to further optimize our design and to adapt it to different application requirements.
Tags: qpace
